Boundary scan with strobed pad driver enable

ABSTRACT

A circuit and a method are provided for testing the enable function of Boundary Scan Register bits that control the driver of unconnected I/O pins of an 1149.1-compliant IC during the IC&#39;s reduced pin-count access manufacturing test, and to test the connections to these pins during the test of a circuit board containing the IC, without causing excessive current if a pin is inadvertently short circuited.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication Ser. No. 60/425,994 filed Nov. 14, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates, in general, to the testing of integratedcircuits (ICs) and, more specifically, to a method and circuit fortesting integrated circuit (IC) output pin circuitry, and connectionsbetween pins of ICs on circuit boards.

2. Description of Related Art

A common way to provide test access to digital pin signals of an IC isto implement digital boundary scan according to the rules defined in the“IEEE Standard Test Access Port and Boundary-Scan Architecture”,published in 1990 and 2001, by the Institute for Electrical andElectronic Engineers (IEEE), which is also known as IEEE Std.1149.1-2001, or simply 1149.1. A dominant characteristic of 1149.1 isthe use of a test access port (TAP) controller that has a prescribedstate diagram, an Instruction Register (IR), and multiple Data Registers(DR), one of which is the Boundary Scan Register (BSR). FIG. 5 is astate diagram which shows all possible states of an 1149.1 TAPcontroller.

Note that bond pads of a bare integrated circuit die are eventuallyconnected to the pins of an encapsulating package. Accordingly, in thepresent disclosure, the terms “pin”, “bond pad” and “pad” will be usedinterchangeably.

Recently, 1149.1 has been shown to be suitable for facilitating reducedpin-count testing of high pin-count ICs, which can significantly reducethe cost of testing the ICs. To enable this method, pin circuitry isfirst made bidirectional by the provision of input buffers 11 and outputdrivers 15 connected to bond pad 17, as shown in FIG. 1, and thenboundary scan circuitry is added, as shown in FIG. 2. The boundary scancircuitry includes a shift register element 19 for testing the enableinput of output driver 15, and a shift register element 21 for testingthe data input of driver 15. Register element 21 includes a storageregister (not shown) for storing an output data value and/or a captureddata value. Output driver 15 is enabled by an enable bit stored inregister element 19. The output data value and/or captured data value isstored in the storage register in register element 21. To permitimplementation of a HIGHZ instruction defined by 1149.1, a slightmodification is needed for the BSR-controlled pad driver circuitry 30 ofFIG. 3, to facilitate simultaneously tristating (disabling) all outputdrivers. The modification comprises an AND gate 23 which receives theoutput of register 19 and an inverted forceDisable (tristating) signal.Thus, when the forceDisable signal is inactive (logic 0), the state ofthe enable input of output driver 15 is determined by the output ofregister 19. An active forceDisable signal is applied to override theoutput of the shift register.

Applicant's U.S. patent application Ser. No. 09/570,412 filed May 12,2000, for “Method and Circuit for Testing D.C. Parameters of CircuitInput and Output Nodes” (Applicant's Docket LVPAT017US), now U.S. Pat.No. 6,586,921 B1 granted on Jul. 1, 2003, incorporated herein byreference, discloses a method by which the simultaneous tristatefunction is tested for unconnected pins of an IC using the timing shownin FIG. 4. In that method, at time t₁, the pins are tri-stated inresponse to an instruction being loaded into the IC. Subsequently, attime t_(D), the data input to the output drivers is changed. Then, attime t₂, the logic value of the pad is captured. If the logic valuechanged in response to the data input change, then the tristatefunctionality is defective (for example, forceDisable is stuck at 0),and the chip fails the test. The sequence of states shown in FIG. 4 isin accordance with 1149.1. This test does not, however, test whether theEnable bit in the BSR is stuck on (due to a defect).

To test circuit boards that contain ICs constructed according to 1149.1,different patterns of output driver logic values are shifted into theICs during the Shift-DR state (the state is re-entered once per bituntil all boundary scan bits have been shifted into all ICs), and theresultant logic value on each I/O interconnect is captured during theCapture-DR state. Then, another set of values is shifted in during thenext transit through the Shift-DR state.

One problem with this test approach is that the minimum duration of thelogic value of each output pin during testing is limited by the timerequired to reload the boundary scan register. For example, if ten ICs,each with a 100 bit boundary scan chain, are connected in series, thenthe time to reload the scan chain is one thousand periods of the testclock TCK during the Shift-DR state of the TAP (see FIG. 5). If theclock period is the typical value of one microsecond, then the minimaltime to reload the scan chain is one millisecond. Although this is ashort time compared to total test time, any high powered pin driversthat are short-circuited for that duration of time may be damaged by theheat generated within its transistors while the abnormally high currentis flowing. In some cases, damage can occur in tens of microseconds, andis sufficient to reduce the expected lifetime of the circuit.

Whetsel U.S. Pat. No. 5,706,296 granted on Jan. 6, 1998 for“Bi-directional Scan Design with Memory and Latching Circuitry” proposesa solution to this problem. The proposal includes providing a latchingaction in the output driver path so that a short circuit causes thedriver to stop driving its intended logic value and switches to drivingthe opposite logic value. This approach requires modifying the driver'scircuitry, to insert a delay in the output path, and may flip thedriver's state if a very low impedance load is connected that is withinspecification.

Terayama U.S. Pat. No. 5,736,849 granted on Apr. 7, 1998 for“Semiconductor Device and Test Method for Connection BetweenSemiconductor Devices” proposes a solution which provides a weak outputdriver and a strong driver connected in parallel. During test mode, onlythe weak driver is enabled. As with the Whetsel solution, this circuitrequires modification of the driver circuitry, and may not be able todrive a very low impedance load that is within specification.

SUMMARY OF THE INVENTION

The present invention seeks to provide a circuit and a method fortesting the function of BSR bits that control the enable input to adriver of unconnected I/O pins of an 1149.1-compliant IC during the IC'sreduced pin-count access manufacturing test, and to test the connectionsto these pins during the test of a circuit board containing the IC,without causing excessive current if a pin is inadvertently shortcircuited when pin drivers are enabled—the excess current being due to adefect or to too many outputs being enabled simultaneously.

The circuit of the present invention is constructed according to 1149.1,and comprises an IC having a first test mode in which data can be loadedinto a BSR without updating the output latches, and a second test modein which the BSR can be accessed and updated while output pin drivers ofthe IC are tristated, and circuitry to temporarily de-assert the signalthat tristates the pin drivers, at the time that the pins' logic valuesare captured by the BSR. “Temporarily” means a clock cycle or less andfor only a portion of the capture-DR state.

The circuit aspect of the present invention is generally defined as aboundary scan interface circuit for use with a test access port (TAP)controller for testing the state of pin drivers of an IEEE1149.1-compliant integrated circuit (IC) having a boundary scanregister, the interface circuit comprising a tristate control circuitfor selectively controlling the pin driver enable input of the pindrivers and responsive to a control input for temporarily de-asserting asignal that tri-states the pin drivers during a capture cycle of the TAPin which pin logic values are captured by the BSR.

The method of the present invention tests that the enable bit path isnot stuck in an ‘on’ state for unconnected pins during reduced pin-counttests of an IC by driving the pins to a selected logic state, thenre-loading the BSR with the opposite enable values and opposite datavalues, simultaneously tristating all pins before updating the outputs,de-asserting the tristate function and capturing the pin logic valueswhile the tristate function is de-asserted.

One embodiment of the method of the present invention is generallydefined as a method of testing an integrated circuit to test thatboundary scan register pin enable bit paths are not stuck in an “on”state, the method comprising: loading desired circuit pin data and pindriver enable data into a boundary scan register and updating theboundary scan register; loading opposite circuit pin data and theopposite pin driver enable data into the boundary scan register andsuppressing updating of the register during a following register updatecycle; forcing output drivers into a high impedance state (tristate);updating the data and enable inputs to the output drivers to the saidopposite logic values during one of a Run-test/idle or a Select-DR stateof a test access port; capturing register outputs; and unloading andcomparing captured outputs with expected outputs to determine whetherany pin enable bit path is stuck in an “on” state.

Another embodiment of the method of the present invention is generallydefined as a method of testing an integrated circuit having a boundaryscan register to determine whether circuit output pins have any shortcircuits between the pins and a power rail, or other high-currentoutput, that might result in the flow of excess current, the methodcomprising: tristating circuit output pins; loading the boundary scanregister with values to force output drivers into desired output states;capturing pin outputs while de-asserting tristating during a capturecycle; and unloading captured data and comparing with expected values.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will become more apparent fromthe following description in which reference is made to the appendeddrawings in which:

FIG. 1 is a prior art schematic of a bidirectional pin of an IC.

FIG. 2 is a prior art schematic of a bidirectional pin of an IC that hasBSR access to and control of the pin.

FIG. 3 is a prior art schematic of a bi-directional pin of an IC thathas BSR access to and control of the pin, and a tri-stating signal thatcan simultaneously tristate all such pin outputs.

FIG. 4 is a set of waveforms for the circuit of FIG. 3 when a prior artmethod is used for testing the tristating signal when the pins are notconnected directly to a tester.

FIG. 5 is a prior art state diagram of the 1149.1 TAP controller.

FIG. 6 is a schematic of a circuit according to one embodiment of thepresent invention.

FIG. 7 shows waveforms of the circuit of FIG. 6 when the circuit is usedto test the tristate signal according to an embodiment of the method ofthe present invention.

FIG. 8 shows alternative waveforms of the circuit of FIG. 6 when thecircuit is used to test the tristate signal according to anotherembodiment of the method of the present invention.

FIG. 9 shows waveforms of the circuit of FIG. 6 when the circuit is usedto test connections to the output driver according to another embodimentof the method of the present invention.

FIG. 10 is a flow chart illustrating a test method for testing thefunction of an enable bit of a pin driver, according to an embodiment ofthe present invention.

FIG. 11 is a flow chart illustrating a test method for testing whetheroutput pins of an IC, that is soldered onto a circuit board, has anyshort circuits between the pins and a power rail, or other high-currentoutput, that might result in the flow of excess current.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the presentinvention, However, it will be understood by those skilled in the artthat the present invention may be practiced without these specificdetails. In other instances, well known methods, procedures, componentsand circuits have not been described in detail so as not to obscureaspects of the present invention.

The circuit of FIG. 6 shows the BSR-controlled pad driver circuitry 30of FIG. 3 connected to a TAP controller 40 similar to the example TAPcontroller shown in the 1149.1 standard. The TAP controller typicallyoutputs ShiftDR, Mode, ClockDR, and UpdateDR signals to control theboundary scan cells which form boundary scan register 42. Additional TAPcontroller outputs include forceDisable, which may be the logic value ofa bit in the Instruction Register, Capture-DR which indicates when theTAP controller is in its Capture-DR state, inverted test clock, TCK; andRTI, which is active (logic 1) when the TAP controller is in theRun-Test/Idle (RTI) state. Many or all of these signals already exist insome TAP controller designs.

The circuit of the present invention is responsive to two more controlsignals provided by two register bits, Q₀ and Q₁, which may be part ofthe TAP instruction register (IR) or part of a data register (DR), butpreferably not the BSR. The bits are shown as isolated single-bitregisters in FIG. 6 to indicate this generality.

The Q₁ bit is a tristate disabling control signal which determineswhether the forceDisable signal is to be de-asserted during a TAPCapture-DR controller state. The Q₀ bit is an update selector controlsignal which determines whether update of the BSR is to be delayed, asexplained below.

The two bits define two test modes according to the present invention.In a first test mode, both bits are active (logic 1). In the secondmode, Q₁ is active and Q₀ is inactive (logic 0).

In both modes, the output driver tristating signal, forceDisable, istemporality de-asserted during BSR capture operations. In the firstmode, the BSR normal update operation is suppressed or delayed until thenext RTI state or select-DR state of the TAP controller. In the secondmode, normal update operations are performed during the Update-DR stateof the TAP.

Referring to FIG. 6, the Q₁ bit is part of a first logic circuit 50which includes a delay element Q₂, in the form of a flip-flop 52, a NANDgate 54 and an AND gate 56.

The Q₁ bit is set to logic 1 to enable de-asserting of the forceDisablesignal (i.e., forcing it to logic 0) during the TAP controllerCapture-DR state when pin logic values are captured by the BSR. NANDgate 54 logically combines the Q₁ bit with a delayed Capture-DR statesignal output by flip-flop 52. Thus, the output of NAND gate 54 is apulse that is one test clock (TCK) period in duration and that isapplied to one input of AND gate 56. AND gate 56 also receives theforceDisable signal and produces a modified forceDisable signal labeledforceDisableBSR. The Capture-DR signal is delayed by half of a TCKperiod so that capture occurs substantially in the middle of the clockperiod within which the tristating signal is de-asserted.

When the TAP controller is in a state other than the Capture-DR state,the output of NAND gate 54 is high (logic 1). The output of AND gate 56then depends on the value of the forceDisable signal. When forceDisableis high, forceDisableBSR is high, the output of AND gate 23 is low and,thus, output driver 15 is tristated or disabled.

The Q₀ bit is part of a second logic circuit 60 which includes an ANDgate 62 and multiplexer 64. When Q₀ is inactive (logic 0), normal updatetiming is selected (i.e., in accordance with 1149.1) by multiplexer 64,which outputs a signal labeled UpdateBSR. When Q₀ is logic 1, themultiplexer selects the output of AND gate 62 which is a delayed Updatepulse which occurs during the RTI state. AND gate 62 logically combinesthe RTI signal and an inverted test clock signal, TCK, to produce apulse that is one half of one test clock period in duration.

First Test Mode

An objective of the present invention is to test that BSR Enable bitpath 34 is not stuck in the “on” state. According to the method of thepresent invention, this is achieved by loading the BSR with pin data andpin driver enable logic values and updating pin outputs; configuring thecircuit in the first test mode; re-loading the BSR with data that wouldcause the output drivers to drive their opposite logic value and totristate the output drivers, without updating BSR latches; applying anoutput driver tristating signal to tristate all pins simultaneously;updating BSR latches; and de-asserting the tristating signal, capturingpin logic values in the BSR, and then re-asserting the tristatingsignal; and unloading the captured data for comparison with expecteddata.

Referring to FIG. 10, an embodiment of the method to accomplish thisobjective comprises:

Step 100 involves loading desired driver data and driver enable bitsinto the BSR and updating the BSR so as to force output drivers to aknown driving state such as, for example, driving logic 1 (while Enableis ‘on’).

Step 102 involves configuring the circuit in a first test mode bysetting both register bits Q1 and Q0 to logic 1 which will suppressfuture updating of BSR latches during the Update-DR state of the TAP,cause future updating of the BSR to occur during the RTI state of theTAP, and de-assert forceDisable during the Capture-DR state. This isachieved by either loading an instruction which includes bits Q1 and Q0or loading an instruction which accesses a separate data register whichincludes bits Q1 and Q0.

Step 104 involves reloading the BSR with data that would cause outputdrivers to drive their opposite logic value and to tristate the outputs(Enable bit is ‘off’). In this step, update of the BSR latches issuppressed because Q₀ was set active in step 102.

Step 106 involves loading an “EXTESTZ” instruction into the TAPcontroller instruction register. This instruction (whose name isarbitrary) is the same, in its effect, as the standard EXTESTinstruction that selects the BSR to be the active DR, and enables theBSR bits to control output drivers, except that the EXTESTZ instructionforces output drivers into their high impedance state (tristate) by anasserted forceDisable signal.

As shown by the waveforms of FIG. 7, the instruction register is updatedwith the EXTESTZ instruction at time t₁, during the Update-IR state ofthe TAP, which tristates the outputs at time t₁, shown byforceDisableBSR becoming active. It will be noted that the waveforms ofFIG. 7 show only the timing-critical portion of the method.

Step 108 involves updating the Data and Enable inputs to the outputdrivers to opposite logic values during the RTI state. Alternatively,this update may occur during the Select-DR state, as shown in FIG. 8, sothat the RTI state is not needed. The delay in performing the update isto ensure that the update of the Pad Data takes effect after theforceDisable signal becomes active.

Step 110 involves de-asserting ForceDisable during the Capture-DR state,preferably for one TCK cycle, and capturing the logic value of the pinsignal by the BSR and shifting out the captured value for comparisonwith an expected value (logic 1 for this example).

Thus, if the pin enable path is stuck “on”, then waveforms 115–118 willoccur and the wrong logic value (logic 0 in this example) will beshifted out, indicating that the related pin-driver was erroneouslyenabled, and so a defect must exist.

The above method may be repeated (step 112), but initially driving thepins to opposite starting values, e.g., to logic 0, instead of logic 1.

Second Test Mode

The present invention also seeks to provide a method of testing whetheroutput pins of an IC that is soldered onto a circuit board has any shortcircuits between the pins and a power rail, or other high-currentoutput, that might result in the flow of excess current. This can beperformed using the above described circuit. This embodiment of themethod of the present invention generally comprises tristating theoutput drivers and then configuring the circuit in the second test mode;loading the boundary scan register with values to force output driversinto desired output states; capturing pin outputs while de-assertingtristating only during the capture cycle; and unloading captured dataand comparing with expected values.

Referring to FIG. 11, this embodiment of the method is as follows.

Step 200 involves setting register bit Q₁ to logic 1, which de-assertsforceDisable during Capture-DR, and register bit Q₀ to logic 0, whichenables normal BSR update operations during the TAP Update-DR state, andforces output drivers into their high impedance state (tristate) by anasserted forceDisable signal. This is achieved by either loading aninstruction for an instruction register that includes bits Q₁ and Q₀ orloading an instruction which accesses a separate data register whichincludes bits Q₁ and Q₀.

Step 202 involves loading bits into the BSR to force output drivers intoselected output states (when the forceDisable signal is de-asserted).When the Update-DR pulse state occurs, as shown in FIG. 9, BSR latchesare updated, but the output drivers remain in high impedance state(shown symbolically as a mid-rail dash-dot waveform 135) because of theactive forceDisable signal.

Step 204 involves temporarily de-asserting the forceDisable signalduring the next Capture-DR state, as shown in FIG. 9, causing the pinsto be driven to their intended output states, and capturing theresultant pin logic values in the BSR.

Step 206 involves unloading the captured bits for comparison to expectedbit values. According to the 1149.1, new data values for subsequenttests may be shifted in simultaneously with shifting out capturedvalues. Captured logic values which differ from expected values indicatea short circuit.

The method of the present invention may be used for testing a circuitboard that has a mixture of circuits, i.e., circuits which incorporatethe interface circuit of the present invention and circuits which donot. The method does not require a change in the protocol used to accessthe BSR of any of the circuits.

In addition to shorts to power rail and high-current output of anycircuit, the method allows safely detecting stuck enable bits inintegrated circuits which do not implement the method of the presentinvention but which are connected to circuits which include thecircuitry of the present invention. This type of fault might be normallydetected by standard 1149.1 boundary scan when a wire is drivensimultaneously by a defect-free circuit and by a defective circuit thathas its enable stuck “on”; however, if the defect-free circuit embodiesthe present invention, high current will flow for much less time andthus cause no damage to the defect-free circuit.

Excess current may flow through a pin for other reasons, includinginadvertent mechanical connections between a wire and other metallicobjects, or due to shorts between wires that travel to other circuitsubstrates. Excess current may also flow through a power rail when toomany output drivers are enabled simultaneously—the present inventiongreatly reduces the time interval during which the excess current flows,and hence reduces the average current.

Although the present invention has been described in detail with regardto preferred embodiments and drawings of the invention, it will beapparent to those skilled in the art that various adaptions,modifications and alterations may be accomplished without departing fromthe spirit and scope of the present invention. Accordingly, it is to beunderstood that the accompanying drawings as set forth hereinabove arenot intended to limit the breadth of the present invention, which shouldbe inferred only from the following claims and their appropriatelyconstrued legal equivalents.

1. A boundary scan interface circuit for pin drivers of an IEEE1149.1-compliant integrated circuit (IC) having a test access port (TAP)controller and a boundary scan register (BSR), said boundary scaninterface circuit comprising: a tristate pin driver that can be enabledby said BSR unless a tristate control signal from said TAP controller isasserted; a first mode control input signal; and a tristate controlcircuit that, when said first mode control input signal is logic 1,temporarily de-asserts said tristate control signal during a capturestate of said TAP controller in which in logic values are captured bythe BSR.
 2. A boundary scan interface circuit as defined in claim 1,further including: a second mode control in input signal; and an updatecontrol circuit that, when said second mode control input signal islogic 1, prevents the BSR from being updated during an update state ofsaid TAP controller and instead, delays the update to another statebefore said capture state.
 3. A boundary scan interface circuit asdefined in claim 1, said tristate control circuit including: first meansfor combining said first mode control input signal, a TAP controllerCapture-DR state signal and a test clock signal to produce a tristatecontrol signal; and second means for combining a tristating signal fromsaid BSR and said tristate control signal to produce a pin driver enablesignal.
 4. A boundary scan interface circuit as defined in claim 3, saidpin driver enable signal being a pulse having a duration of one clockperiod of a test clock.
 5. A boundary scan interface circuit as definedin claim 2, said update control circuit including: first means forcombining a test clock signal and a TAP controller Run-test/idle statesignal to produce a delayed update control signal; and second meansresponsive to said second mode control input signal for selectingbetween a TAP controller Update-DR state signal and said delayed updatecontrol signal to produce an update signal to said BSR.
 6. A boundaryscan interface circuit for use with a test access port (TAP) controllerfor testing the state of pin drivers of an IEEE 1149.1-compliantintegrated circuit (IC) having a boundary scan register (BSR), saidinterface circuit comprising: a tristate control circuit for selectivelycontrolling a pin driver enable input of said pin drivers and responsiveto a control input for temporarily de-asserting a signal that tri-statesthe pin drivers during a capture cycle of said TAP in which pin logicvalues are captured by the BSR; an update control circuit responsive toa second control input for generating a boundary scan cell update signalto provide a first test mode for loading test data into a boundary scanregister without updating outputs of said register; said update controlcircuit including means for combining a test clock signal and a TAPRun-test/idle state signal for producing a delayed update controlsignal; and means responsive to a test mode control signal for selectingbetween a TAP Update-DR state signal and said delayed update controlsignal for providing an update signal to said BSR.
 7. A boundary scaninterface circuit as defined in claim 6, said update control circuitincluding: means for combining a test clock signal with one of a TAPcontroller run-test/idle state signal and a TAP controller select-DRstate signal to produce a delayed BSR update control signal; and aselector responsive to a test mode control signal for selecting betweena TAP update signal and said delayed control signal.